The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design rules of 0.18 .mu.m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional junction and contact formation technology, including photolithographic, etching, and deposition techniques.
As a result of the ever increasing demand for large-scale and ultra-small dimensioned integrated semiconductor devices, self-aligned techniques have become the preferred technology for forming such devices in view of their simplicity and capability of high-density integration. As device dimensions decrease, both vertically and laterally, many problems arise, especially those caused by an increase in sheet resistance of the contact areas to the source and drain regions and junction leakage as junction layer thickness decreases. To overcome this problem, the use of highly electrically conductive refractory metal silicides has become commonplace in the manufacture of integrated semiconductor devices comprising, e.g., MOS type transistors. Another technique employed in conjunction with refractory metal silicide technology is the use of lightly doped drains ("LDDs"). An LDD consists of a lightly doped source/drain region (i.e., dopant density is on the order of about 9.times.10.sup.19 at/cm.sup.3) formed just at the edge of the gate region, while a more heavily doped drain region (i.e., dopant density is on the order of about 2.times.10.sup.20 at/cm.sup.3), to which ohmic contact is to be provided, is laterally displaced away from the gate by provision of a sidewall spacer on the gate electrode.
Salicide processing involves deposition of a metal that forms an intermetallic compound with silicon, but does not react with silicon oxides or silicon nitrides under normal processing conditions. Refractory metals commonly employed in salicide processing include titanium, nickel, and cobalt, each of which form very low resistivity phases with silicon, e.g., TiSi.sub.2, NiSi.sub.2, and CoSi.sub.2. In practice, the refractory metal is deposited in a uniform thickness over all exposed upper surface features of the silicon wafer, preferably by means of physical vapor deposition (PVD) from an ultra-pure sputtering target and an ultra-high vacuum, multi-chamber DC magnetron sputtering system. In MOS transistor formation, deposition is generally performed both after gate etch and after source/drain junction formation. After deposition, the refractory metal blankets the polysilicon gate electrode, the silicon oxide or nitride spacers, the silicon oxide isolation regions, and the exposed portions of the source and drain regions. As a result of a rapid thermal annealing (RTA) process performed in an inert atmosphere, the refractory metal reacts with underlying silicon to form electrically conductive silicide layer portions on the top surface of the gate electrode and on the exposed portions of the source and drain regions. Unreacted portions of the refractory metal layer, e.g., on the silicon oxide or silicon nitride sidewall spacers and the silicon oxide isolation regions, are then removed, e.g., by use of a wet etch process which is selective to the metal silicide portions. In some instances, e.g., with cobalt, a first RTA step may be performed at a relatively low temperature from about 400.degree. C. to about 550.degree. C. for from about 20 sec to about 120 sec in order to form first-phase CoSi which is then subjected to a second RTA step performed at a relatively high temperature from about 700.degree. C. to about 850.degree. C. for from about 20 sec to about 60 sec to convert the CoSi to second-phase, lower resistivity CoSi.sub.2. The second RTA step is performed after selective etch of the non-reacted cobalt. While titanium (Ti) is presently the most prevalent metal utilized in the IC industry for salicide processing, it has a drawback in that titanium silicide (TiSi.sub.2) sheet resistance rises dramatically due to narrow-line effects. As a consequence, the use of cobalt silicide (CoSi.sub.2) has increased as a result of its replacement of titanium silicide in salicide processing. Second-phase cobalt silicide (CoSi2) advantageously does not display narrow-line effects because it forms by a diffusion reaction mechanism rather than by the nucleation-and-growth mechanism observed with titanium silicide. See, for example, European Patent 0651076.
The formation of the sidewall spacers in accordance with conventional refractory metal silicide technology may adversely affect the quality of the silicide that is subsequently formed in later processing steps. The damage occurs to the silicon and polysilicon surfaces during the plasma etching of the spacer material layer, typically a low temperature oxide, to remove the undesired spacer material that has been conformally deposited over the wafer.
Another problem arising from the etching process is the introduction of contaminants to the previously pure silicon and polysilicon surfaces. Like surface damage, the contaminants negatively impact the quality of subsequently formed silicide.
The surface damage and/or the contaminants created in the silicon and polysilicon surfaces by the plasma etching of the spacer material layer will adversely affect the quality of the silicide, since the silicide will be formed in part from the damaged silicon and polysilicon. The lower quality of the silicide is manifested by a decrease in the structural integrity of the silicide and a higher electrical resistance. This has the unfortunate consequence of lowering the overall speed of the semiconductor chip, or in extreme circumstances, threatening the operation of the chip.
There is a need for a method of forming silicide following the formation of sidewall spacers by plasma etching, in a manner that improves the quality of the silicide that is formed.